Intel today announced a breakthrough in making "3D chips". This is being misconstrued by many news outlets as meaning chips that are built out of 3D bricks of logic gates. Actually it's nothing of the sort. These chips are fundamentally 2D (or close to 2D) in layout, they just have conductive rails with U-shaped 3D cross sections. This makes for better transistors because the feature sizes they're working with today are already approaching the size of X-ray wavelengths, meaning it's getting harder and harder to manufacture conductive elements that are unbroken and not "blobby" using lithography. Giving the rails a U-shaped cross section triples the available conductive area, and gives you rails that are more uniform and less blobby in profile view, which means you get less random variance in the resistance of each wire, etc. So we have a factor of 3 improvement in area, and maybe a factor of 10 improvement in uniformity of current flow. That should give us, maybe, 10 more years' jump on Moore's Law ;)
Yes, this is a big manufacturing achievement, but as stated above, these are not 3D chips. However anything that can be done to get out of a single 2D plane is a huge step forward in terms of graph layout: you can't embed any graph that has a subgraph of K_3,3 (bipartite graph with 3 nodes in each part) or K_5 (completely connected graph with 5 nodes) into the 2D plane -- which is exactly why with roads, we have intersections and traffic jams -- except in the case of freeways, which to achieve unimpeded flow are often a spaghetti mess of raised bridges. And this is also why we need flying cars.
So current chips already are not truly 2D or you simply could not produce them, it would be mathematically impossible. There are at least 3 layers of silicon (because that's how you create a transistor anyway). On a macro scale, most motherboards these days have something like 10-15 layers, because that's the only feasible way to lay all the wires. The more layers you can add, the less constrained you are in the layout. So we really just need to be figuring out ways to stack maybe 10-15 layers of silicon and we'd have a huge win.
I suspect that with truly 3D chips -- were you try to pack all the gates into a volume that's closer to a cube than a chip -- the biggest problems will be power density issues, and those issues will be major. We already can't wick away heat fast enough, and with today's (nearly-) 2D chips, the surface area to volume ratio (which is the critical aspect for heat transfer) is already maximized. So chips would have to run far more slowly if they were 3D in structure. (This is why the brain operates at something like 200 Hz and is massively parallel -- but it also only consumes something like 0.5W of power, so it is billions of times more energy efficient than today's computers). On the up-side, all the interconnected parts of a truly 3D chip would be physically closer together, so data path lengths would be much smaller than with current chips.
This is one huge advantage of the brain -- that wires don't have to deal with 2D crossings issues, and can dramatically reduce interconnect distances -- and this is also why if our brains were 4D they could operate much, much faster: in fact if we had 3D neurons embedded in a 4D space, all pairs of neurons could be interconnected with an axonal distance of close to zero :-)
From an energy density and energy efficiency standpoint though, the brain is looking more and more amazing all the time...